7 #ifndef __MSP430WARE_EUSCI_B_SPI_H__
8 #define __MSP430WARE_EUSCI_B_SPI_H__
12 #ifdef __MSP430_HAS_EUSCI_Bx__
32 typedef struct EUSCI_B_SPI_initMasterParam {
38 uint8_t selectClockSource;
40 uint32_t clockSourceFrequency;
42 uint32_t desiredSpiClock;
57 uint16_t clockPolarity;
64 } EUSCI_B_SPI_initMasterParam;
71 typedef struct EUSCI_B_SPI_initSlaveParam {
86 uint16_t clockPolarity;
93 } EUSCI_B_SPI_initSlaveParam;
101 typedef struct EUSCI_B_SPI_changeMasterClockParam {
103 uint32_t clockSourceFrequency;
105 uint32_t desiredSpiClock;
106 } EUSCI_B_SPI_changeMasterClockParam;
116 #define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00
117 #define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT UCCKPH
125 #define EUSCI_B_SPI_MSB_FIRST UCMSB
126 #define EUSCI_B_SPI_LSB_FIRST 0x00
136 #define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH UCCKPL
137 #define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00
145 #define EUSCI_B_SPI_CLOCKSOURCE_ACLK UCSSEL__ACLK
146 #define EUSCI_B_SPI_CLOCKSOURCE_SMCLK UCSSEL__SMCLK
154 #define EUSCI_B_SPI_3PIN UCMODE_0
155 #define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH UCMODE_1
156 #define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW UCMODE_2
164 #define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x0000
165 #define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE UCSTEM
175 #define EUSCI_B_SPI_TRANSMIT_INTERRUPT UCTXIE
176 #define EUSCI_B_SPI_RECEIVE_INTERRUPT UCRXIE
184 #define EUSCI_B_SPI_BUSY UCBUSY
185 #define EUSCI_B_SPI_NOT_BUSY 0x00
210 extern void EUSCI_B_SPI_initMaster(uint16_t baseAddress,
211 EUSCI_B_SPI_initMasterParam *
param);
231 extern void EUSCI_B_SPI_select4PinFunctionality(uint16_t baseAddress,
232 uint16_t select4PinFunctionality);
247 extern void EUSCI_B_SPI_changeMasterClock(uint16_t baseAddress,
248 EUSCI_B_SPI_changeMasterClockParam *
param);
267 extern void EUSCI_B_SPI_initSlave(uint16_t baseAddress,
268 EUSCI_B_SPI_initSlaveParam *
param);
292 extern void EUSCI_B_SPI_changeClockPhasePolarity(uint16_t baseAddress,
294 uint16_t clockPolarity);
309 extern void EUSCI_B_SPI_transmitData(uint16_t baseAddress,
324 extern uint8_t EUSCI_B_SPI_receiveData(uint16_t baseAddress);
345 extern void EUSCI_B_SPI_enableInterrupt(uint16_t baseAddress,
367 extern void EUSCI_B_SPI_disableInterrupt(uint16_t baseAddress,
389 extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint16_t baseAddress,
407 extern void EUSCI_B_SPI_clearInterrupt(uint16_t baseAddress,
423 extern void EUSCI_B_SPI_enable(uint16_t baseAddress);
438 extern void EUSCI_B_SPI_disable(uint16_t baseAddress);
452 extern uint32_t EUSCI_B_SPI_getReceiveBufferAddress(uint16_t baseAddress);
466 extern uint32_t EUSCI_B_SPI_getTransmitBufferAddress(uint16_t baseAddress);
483 extern uint16_t EUSCI_B_SPI_isBusy(uint16_t baseAddress);
MPU_initThreeSegmentsParam param